1. Technical Field
The present invention generally relates to a semiconductor memory apparatus, a test circuit, and method of a semiconductor memory apparatus.
2. Related Art
FIG. 1 is a block diagram of a conventional semiconductor memory apparatus.
The semiconductor memory apparatus includes a plurality of memory banks each storing data in memory cells thereof. The semiconductor memory apparatus may write data into the respective memory banks through an input/output pad, and read data stored in the memory banks through the input/output pad.
Referring to FIG. 1, the semiconductor memory apparatus includes a first bank 1, a second bank 2, and an output unit 5. Data stored in a plurality of memory cells inside the first and second banks 1 and 2 are transmitted to the output unit 5 through global lines GIO<0:3> (i.e., GIO<0>, GIO<1>, GIO<2>, GIO<3>). That is, since the first and second banks 1 and 2 share the global lines GIO<0:3>, the respective memory banks may be accessed through the global lines GIO<0:3>. The output unit 5 aligns the data transmitted through the global lines GIO<0:3> and outputs the aligned data to the outside through input/output pads DQ<0:1> (i.e., DQ<0>, DQ<1>). For example, the data loaded in the first and second global lines GIO<0:1> may be aligned and outputted to the first input/output pad DQ0, and the data loaded in the third and fourth global lines GIO<2:3> may be aligned and outputted to the second input/output pad DQ1.
Also, most of the memory cell failures in the semiconductor memory apparatus are single bit failures. When the single bit failures are sequentially tested one by one to verify whether a single bit failure occurred or not, it is very inefficient in terms of the test time and the test cost. Therefore, the necessity for a test circuit capable of checking whether or not a failure occurred in a memory chip within a short time has increased, and a multi-bit parallel test circuit has been implemented according to the necessity. The multi-bit parallel test circuit preferentially writes the same data into all memory cells within a semiconductor memory apparatus, reads the data stored in the memory cells at a time, and compares the read data. Accordingly, when reading data in a different state, the multi-bit parallel test circuit may detect a failure. That is, the multi-bit parallel test circuit does not check the data outputted through the plurality of global lines one by one through the input/output pads, but checks compressed data outputted through a part of the global lines through a part of the input/output pads. Therefore, it is possible to simply and quickly perform a memory cell test.
As described above, a memory cell failure may be relatively simple to perform through the above-described test circuit. However, in order to secure the operation reliability of the semiconductor memory apparatus, the data output path as well as the memory cell failure needs to be verified in various manners. For example, when a physical failure occurs in global lines during a semiconductor fabrication process, the physical failure will need to be verified. That is, there is a demand for various test circuits for increasing the reliability of the semiconductor memory apparatus as well as the memory cell test.